Forth Day 2010

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Forth Day 2010 Meeting Notes (including slides) are posted here.

Chairman's Welcome - George Perry
Video - 1.30 Mb ogm file

eP32 on the Lattice XP2 Brevia Development Kit - CH Ting
Lattice is selling the XP2 Brevia Development FPGA kit for $29. Ting is working on porting eP32 to this kit, and will report on his progress. The FPGA synthesis, programming, and simulation tools are very different from the familiar ones provided by Xilinx and Altera, so he'll be experiencing the challenges of implementing a Forth engine on this new platform.
Video - 35.6 Mb ogm file
Video - John Rible: RAFT t-shirt presentation - 1.29 Mb ogm file

Low Cost Netbooks - Bill Kibler
Video - 21.1 Mb ogm file

Follow Up to "OO Extensions Considered Harmful" - Samuel A. Falvo II
The plurality of Object Oriented extensions makes reusing 3rd-party packages unnecessarily complex. Sam will show another coding pattern illustrating how you can write reusable components in plain Forth, with surprising results suggesting it's actually more powerful and even more reusable than what object orientation provides.
Video - Kevin Appert introduction - 889 Kb ogm file
Video - 42.4 Mb ogm file

Update: Porting Gforth to eCos - John E. Harbold
John has been able to get Redboot to boot under an i386 KVM virtual environment. Now he's analyzing the Gforth engine to see how to "shoe-horn" it into the eCos source tree.
Video - 86.1 Mb ogm file

J1: A Small Forth CPU Core for FPGAs - James Bowman
James will describe a 16-bit Forth CPU core, intended for FPGAs. The instruction set closely matches the Forth programming language, simplifying cross-compilation. Because it has higher throughput than comparable CPU cores, it can stream uncompressed video over Ethernet using a simple software loop. The entire system (source Verilog, cross compiler, and TCP/IP networking code) is published under the BSD license. The core is less than 200 lines of Verilog, and operates reliably at 80 MHz in a Xilinx Spartan(R)-3E FPGA, delivering approximately 100 ANS Forth MIPS.
Video - 42.8 Mb ogm file

Introducing SwiftCore - Leon Wagner and Brad Eckert
The SwiftCore SC20 is a 32-bit soft CPU designed for SoC applications. Its architecture is equally at home in ASICs and FPGAs, and is compatible with FPGA block RAMs. The instruction set architecture (ISA) is stack oriented and close to native Forth, so it doesn't need a sophisticated optimizer for high performance. The ISA also supports signed and unsigned 8-bit, 16-bit, and 32-bit data types with base+offset addressing modes, frame stacks, and temporary registers. We will demonstrate an instantiation of the SC20 on the Lattice XP2 Brevia development kit along with the interactive SwiftX cross compiler.
Video - 110 Mb ogm file

Update on GreenArrays - Staff

  • Introduction, Status, and Plans - Greg Bailey
    Video - 41.7 Mb ogm file
  • Using S40 to Build Mobile Robot Vision - Michael Montvelishsky
    Video - 61.8 Mb ogm file
  • Development Cycle Overview - Jeff Fox
    Video - 46.8 Mb ogm file
  • Softsim & Testbeds - Charley Shattuck and John Rible
    Video - 16.3 Mb ogm file
  • Debugging - Jeff Fox
    Video - 18.5 Mb ogm file
  • Chip Testing - Steven Hsu
    Video - 29.2 Mb ogm file
Fireside Chat - Chuck Moore
Video - 79.6 Mb ogm file

Rollcall of those attending Forth Day 2010
Video - 5.02 Mb ogm file