* Simulation of CMOS Logic and Amplifier

* C. H. Ting, 4/19/2005

.control
destroy all
run
plot out1+30 out+24 set+18 clr+12 in1+6 in2
*plot out+12 in1+6 in2
*plot out+6 in1
.endc
 
.tran 60p 100n 10p UIC

*****	Input signals
vdd	vdd	0	DC	5
Vin1	in1	0	DC	0	PULSE 0 5 0 0 0 10n 20n
Vin2	in2	0	DC	0	PULSE 0 5 0 0 0 2n 4n
Vset	set	0	DC	0	PULSE 0 5 0 0 0 20n 40n
Vclr	clr	0	DC	0	PULSE 0 5 0 0 0 40n 80n

*****	Subcircuit definitions

X22 in1 in2 set clr out out1 DFF
.subckt DFF d clock set clear q qbar
X10	clock	clockb	inv
XN1	in1	clear	q1	NAND
XN2	q1	set	qbar1	NAND
XT1	d	in1	clockb	tg
XT2	qbar1	in1	clock	tg
XN3	in2	set	q	NAND
XN4	q	clear	qbar	NAND
XT3	q1	in2	clock	tg
XT4	in2	qbar	clockb	tg
.ends

*x21 1n1 in2 out set INTEGRATE
.subckt INTEGRATE in1 in2 out control
x1 in1 in out OPAMP
r1 in2 in 1k
r2 out in r=v(control)>1 ? 1meg : 50
c1 out in 5p
.ends

*x11 in1 in2 out OPAMP
.subckt OPAMP in1 in2 out
e1 out 0 in1 in2 100000
.ends 

*x12 in1 in2 out COMPARE
.subckt COMPARE in1 in2 out
e1 out 0 value=if((v(in1)>v(in2)), 5, 0)
.ends

*x12 in1 in2 out1 out2 COMPARE2
.subckt COMPARE2 in1 in2 out1 out2
e1 out1 0 value=if((v(in1)>v(in2)), 5, 0)
e2 out2 0 value=if((v(in1)>v(in2)), 0, 5)
.ends

*x13 in1 in2 out NAND
.subckt NAND in1 in2 out
e1 out 0 value=if((v(in1)>2.5 && v(in2)>2.5), 0, 5)
.ends

*x14 in1 in2 out NOR
.subckt NOR in1 in2 out
e1 out 0 value=if((v(in1)>2.5 || v(in2)>2.5), 0, 5)
.ends

*x15 in1 in2 out XOR
.subckt XOR in1 in2 out
e1 out 0 value=if((v(in1)>2.5 == v(in2)>2.5), 0, 5)
.ends

*x16 in1 out INV
.subckt INV in out
e1 out 0 value=if((v(in)>2.5), 0, 5)
.ends

*r1 out in1 1k
*x17 out 0 in2 TG
.subckt TG outp outn in 
r1 outp outn r= v(in)>2 ? 50 : 1meg 
c1 outp 0 1e-12
c12 outn 0 1e-12
.ends

.end