09:39:04	 From  Juergen Pintaske : Thanks for the meeting, 
but the dog now forces me to leave …
Will try to come back later
09:44:48	 From  Bob Armstrong : All the float fns in CoSy , including I/o are in https://cosy.com/4thCoSy/Code/lib/math/floats .

Alignment etc in CoSy is essentially trivial for any strings .
What it really needs is exponential output , which I offer as a challenge .
10:05:44	 From  Dave Jaffe : For folks in the SF Bay Area - the Electronics Flea Market returns starting on Sun, April 16th and the 2nd Sundays subsequently at West Valley College Parking Lot 3 - see https://www.electronicsfleamarket.com/
10:24:17	 From  Kevin Appert : Don, you're up in a few minutes...
10:24:20	 From  Kevin Appert : ready?
10:25:36	 From  Don Golding : yes
10:26:18	 From  Brett Gordon IST : Reacted to "yes" with 👍
10:28:49	 From  Kevin Appert : 😎
10:45:10	 From  Bob Armstrong : An interesting related paper from the APL side recently learned of : Tensors Come of Age , Why the AI revolution will help HPC 
https://arxiv.org/ftp/arxiv/papers/1709/1709.09108.pdf
11:05:11	 From  Bob Armstrong : The point of CoSy APL level notation in open Forth is to be able to write 
A B f and have f applied to all corresponding nodes of trees , lists of lists , the notion of " atomic apply " from APL .
Open Forth for the flexibility to map to , eg: CORE1 FPGA .
11:15:15	 From  M Edward Borasky (@znmeb) : This FPGA stuff looks so cool but I promised myself I'd finish the two audio projects I have now. :-)
11:16:31	 From  M Edward Borasky (@znmeb) : There are commercial synthesizers with FPGAs inside though.
11:36:14	 From  Kevin Appert : Andy, nice to see you!
11:38:04	 From  Kevin Appert : "Begs the question" doesn't mean what it used to mean.
11:40:04	 From  Marc Petremann : Real-time animated clock with eFORTH web https://eforth.arduino-forth.com/article/examples_web_clock
11:40:58	 From  Kevin Appert : Does it get time-of-day from GPS, the web, or WWV?
11:41:52	 From  Marc Petremann : It's get time from your computer
11:42:27	 From  M Edward Borasky (@znmeb) : I'd buy one after Labor Day for audio :-)
11:43:12	 From  Christopher Lozinski : What is your low latency application?
11:43:22	 From  Marc Petremann : If you will see FORTH code, i's simple: right-clic with mouse and select "page code source"
11:44:49	 From  M Edward Borasky (@znmeb) : Yeah, most of the DACs are I2S, which would be done in System Verilog
11:47:26	 From  Kevin Appert : arduinos in space?  Sounds Sketchy.
11:53:02	 From  Andrew Korsak : Nice to see you too, Kevin, Bill, Dave. I don't recall seeing any of the others at SvFig meetings at Stanford.  It's good that SvFig is continuing these meetings. I haven't participated much because I have been too busy with my ham radio direction finding project using Gforth on an RPi3B.
11:55:15	 From  Bob Armstrong : Reacted to ""Begs the question" ..." with 👍
11:56:23	 From  Don Golding : Lattice FPGA iCE40 Ultra Plus 5K
11:56:35	 From  Don Golding : 5$ FPGA
11:57:47	 From  Don Golding : https://www.mouser.com/ProductDetail/Lattice/ICE40UP5K-SG48I?qs=Rp3RbKSfAt3UqOG1AN4%2FAg%3D%3D