CamelForth on a VHDL 1802 core in an FPGA
notes for SVFIG presentation, 23-JAN-2010
Eric Smith <eric@brouhaha.com>


RCA CDP1802 microprocessor

introduced in 1976, for under $30
first single-chip CMOS microprocessor
	very low power
	available in SOS version, radiation hardened
		very suitable for space applications
		used in satellites
COSMAC Elf project in Popular Electronics
	commercial RCA VIP, Netronics Elf 2, Quest SuperElf, etc.
	recent Elf 2000 by Spare Time Gizmos (includes a Forth)
still sold today by Intersil

8-bit processor (8-bit ALU, accumulator)
16 16-bit registers useful as index registers

interesting features:
	PC is a general register (like PDP-11)
		but ANY of the R registers can be the PC
			specified by the P registers
			changed on the fly by SEP instruction
			fast interrupts, context switching,
				subroutine calls (non-reentrant)	
	built-in DMA controller
	"load mode" makes it easy to bootstrap from
		front panel switches

weaknesses:
	slow - 3.2 MHz
		machine cycle is 8 clocks
		instructions take 2 or 3 machine cycles (16 or 24 clocks)
	no real stack
		calling convention using software stack,
			but has high overhead

several Forth implementations
	recent: CamelForth (ANS Forth)
		http://camelforth.com/
	ported to 1802 by Harold Rabbie

VHDL implementation of 1802 core
	tested by simulation with GHDL
	uses under 350 logic elements (LUT, FF) in Spartan 3E FPGA
	most instructions validated (a few yet to be done)
	running on a Spartan 3E-1600 eval board
		(has around 30,000 logic elements)
	Spartan 3E-1600 has 34 on-chip BlockRAMs, 2KB each, which
		can be used for 64KB of memory with 2 left over

advantage of FPGA:
	much faster than real 1802
	runs at 25 MHz in the slow speed grade of the Spartan 3E
	however, actually *much* faster!
	VHDL 1802 needs only one clock cycle per machine cycle,
		so only 2-3 clocks per instruction vs. 16-24
	effectively equivalent to a 200 MHz CDP1802,
		more than 60x faster than the original chip

disadvantage of FPGA:
	much higher power consumption (even per instruction executed)

Peripherals on FPGA:
	UART
	video display to VGA monitor
		emulation of CDP1861 "Pixie" graphics (max 64x128)
		not yet fully implemented

possible future additions:
	CF or SD flash interface
	additional instructions of CDP1804/1805/1806

CamelForth for 1802
	originally used PseudoSAM shareware assembler (very old)
	ran on an 1802 simulator supplied with the CamelForth port
	hacked to assemble with ASL open-source assembler
		a few gotchas, such as "DUP" having special meaning in ASL
			so ".dw dup" doesn't work, had to change symbol name
	verified byte-for-byte identical with PseudoSAM output
	modified for VHDL system to use UART